On March 4, according to a number of supply chain enterprises, Nvidia is suspected of adjusting its CoWoS advanced packaging order volume issued to TSMC after the announcement of bright financial results in the fourth quarter. It is worth noting that the two sides previously negotiated outsourcing cooperation for the Chip on Wafer (CoW) packaging process in the previous segment, and ultimately failed to reach a substantive agreement. This series of developments in the capital market caused continuous shocks, a number of investment institutions have begun to re-evaluate the valuation model of the relevant companies.
"The company does not comment on the status of any customer orders," a TSMC spokesperson told TIME on March 2, in response to market rumors. However, this official response did not quell market doubts, and industry analysts began to analyze the deep changes in the industrial chain.
First, the technical iteration logic behind the fluctuation of orders
According to sources familiar with the supply chain, the current TSMC COWOS-related production capacity is still in short supply, and the so-called "order reduction" is essentially a normal adjustment of the iteration period of new and old products. It is worth noting that Nvidia's soon-to-be-discontinued Hopper architecture series chips (including H100, H200, etc.) and the new generation of Blackwell architecture products have significant differences in packaging technology requirements. "The CoWoS-L technology used in the Blackwell series requires the integration of the local silicon intermediate layer (LSI) and redistribution layer (RDL) dual processes, resulting in an overall yield reduction of approximately 20 percentage points compared to the mature CoWoS-S technology," said the senior packaging engineer.
Second, the capacity pain brought about by technological upgrading
Sources in the closed test field confirm that TSMC's advanced packaging production line is currently going through a technology transition period. CoWoS-L's current 70-80% yield level is indeed a significant gap compared to the 99% perfect performance of the previous generation technology. This technology gap directly resulted in a decline of about 30% in effective output per month, but this is a normal fluctuation in the process of technology upgrading. It is worth noting that TSMC has launched a multidimensional response plan including equipment upgrading and process optimization, and the yield is expected to increase to more than 85% in the third quarter.
Third, the strategic layout under the industrial ecological restructuring
At the corporate briefing in January, TSMC CEO Wei Che-jia stressed in particular: "Many rumors about capacity adjustment are untrue, and the company is continuing to expand advanced packaging capacity through global layout." Nvidia CEO Jen-Hsun Huang said more clearly at the latest earnings conference: "The demand curve of the Blackwell series is much higher than expected, and the supply chain issue has been fundamentally resolved." These high-level statements are in stark contrast to market rumors, revealing the information asymmetry of the industrial upgrading period.
It is worth noting that some customers have begun to deploy next-generation fan-out panel level packaging (FOPLP) technology. "The advantages of FOPLP in cost control and packaging efficiency make it an important supplement to 2.5D packaging," said the technical director of a large packaging plant. This diversified choice of technical route has objectively exacerbated the market's misjudgment of traditional CoWoS production capacity.
At present, the semiconductor industry is undergoing a strategic transformation from process miniaturization to system-level innovation, and advanced packaging technology has become the core battlefield of this transformation. Although short-term production capacity fluctuations have caused market concerns, the technical reserves and strategic layout of industrial giants are saving energy for the next round of innovation cycle.
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